Semiconductor package
US7042078B2 · kind B2 · utility
0Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Jun 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes spacers, a chip, bonding wires, contacts, and an encapsulant. The chip is disposed on the spacers. The bonding wires are electrically connected to the chip, and the contacts are electrically connected to the bonding wires. The contacts are electrically connected to an external circuit board. The encapsulant encapsulates the spacers and the active and back surfaces of the chip so as to lower the thermal stress of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.