Method and apparatus for synchronous signal transmission between at least two logic or memory components
US7043653B2 · kind B2 · utility
3Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | May 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.