Multi-chips bumpless assembly package and manufacturing method thereof
US7045391B2 · kind B2 · utility
29Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Aug 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chips bumpless assembly package with a patterned conductive layer, a patterned dielectric layer and an insulation layer interposed between the chips is provided, which can shorten the distance of the electrical connection between the chips so as to upgrade the electrical performance of the assembly package and make the package thinner and thinner. Moreover, a manufacturing method thereof is also provided to form a package with high electrical performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.