Via electromigration improvement by changing the via bottom geometric profile

US7045455B2 · kind B2 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Beichao Zhang · Singapore, SG
• Chun Hui Low · Kluang, MY
• Hong Lim Lee · Bukit Mertajam, MY
• Sang Yee Loong · Singapore, SG
• Qiang Guo · Tangxia, CN

Key dates

• Filing date: Oct 23, 2003
• Grant date: May 16, 2006
• Expiry date: Oct 23, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76814
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.