Semiconductor integrated circuit device and a method of manufacturing the same
US7045848B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Mar 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as a drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of a reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.