Page buffer of flash memory device and data program method using the same
US7046554B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2004 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a page buffer of a flash memory device and data program method using the same. After two data are sequentially stored in a main register (first latch) and a cache register (second latch) provided in a page buffer, they are respectively transferred to an even bit line and an odd bit line at the same time, and a bias needed for a program is applied to cells connected to the even bit line and the odd bit line, respectively, whereby the program is performed at the same time. Therefore, the number and time of operations for data loading, program operation and program verification can be reduced by half and the operating speed of the device can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.