Low power manager for standby operation of memory system
US7046572B2 · kind B2 · utility
5Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Apr 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.