Semiconductor heterostructures and related methods
US7049627B2 · kind B2 · utility
84Cited by
153References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Nov 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.