Pillar cell flash memory technology
US7049652B2 · kind B2 · utility
69Cited by
19References
24Claims
0Family size
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Key dates
| Filing date | Dec 10, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.