Phase change memory device
US7050328B2 · kind B2 · utility
55Cited by
6References
25Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 18, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Feb 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.