Memory array operating as a shift register
US7051153B1 · kind B1 · utility
12Cited by
13References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected between the output of the first column of memory cells and the input of the second column of memory cells. The memory array can be operated as a shift register by shifting data from the first column of memory cells to the second column of memory cells through the multiplexer rather than using general routing lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.