Memory device with barrier layer
US7053445B1 · kind B1 · utility
7Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2005 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Aug 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A memory device may include a substrate, a dielectric layer formed on the substrate and a charge storage element formed on the dielectric layer. The memory device may also include an inter-gate dielectric formed on the charge storage element, a barrier layer formed on the inter-gate dielectric and a control gate formed on the barrier layer. The barrier layer prevents reaction between the control gate and the inter-gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.