System for testing and burning in of integrated circuits
US7053644B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2879
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for testing integrated circuits is described. A contactor board of the system has pins with ends that contact terminals on a power and signal distribution board. Opposing ends of the pins make contact with die terminals on an unsingulated wafer. The distribution board also carries a plurality of capacitors, at least one capacitor corresponding to every die on the unsingulated wafer. Each capacitor may include two substantially flat planar capacitor conductors and a dielectric layer between the capacitor conductors. Alternatively, the capacitors may be discrete components mounted to and standing above the distribution board, in which case corresponding capacitor openings are formed in the contactor substrate to accommodate the capacitors when the distribution board and the contactor board are brought together. A plurality of fuses made of a polymer material are also provided. The polymer material limits the flow of current flowing therethrough when the temperature of a fuse increases, and increases the current therethrough when the temperature of the fuse decreases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.