Datapath architecture for high area efficiency
US7054178B1 · kind B1 · utility
418Cited by
11References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Jun 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A particular DRAM data path architecture is disclosed. In accordance with this invention, the sharing of MDQ sense amplifiers simplifies the circuit design of the memory sub array. Fewer MDQ sense amplifiers and fewer unique MDQ lines leads to a reduced chip layout area. The high address bit of the word line row address (RA) is used to select a particular main data sense amp by means of a control switch. Not only are the sense amplifiers multiplexed for the new sub array, but the data I/O are multiplexed as well, leading to a significant reduction in the number of circuits required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.