Write address synchronization useful for a DDR prefetch SDRAM
US7054222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.