Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US7056807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Aug 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.