Nonvolatile semiconductor memory device employing transistors having different gate withstand voltages for enhanced reading speed
US7057230B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 22, 2002 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jul 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.