Test system for integrated circuits with serdes ports

US7058535B2 · kind B2 · utility

Assignee

• Credence Systems Corporation · US

Inventors

• Gordon Edward Chenoweth · Portland, US
• Marc Loranger · Livermore, US
• Steven R. Payne · Hillsboro, US
• James Kaylor Larson · Portland, US
• Patricia Renee Justice · Portland, US

Key dates

• Filing date: Feb 12, 2004
• Grant date: Jun 6, 2006
• Expiry date: Mar 31, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31713
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.