Apparatus and method for clock domain crossing with integrated decode
US7058799B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Mar 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for transferring signals between timing domains. The apparatus includes a receiver for receiving signals operative in a first timing domain, a decoder for at least partially decoding the signals to generate at least one decoded signal, and an output timing register for outputting the at least one decoded signal in a second timing domain. The signals transferred from the first timing domain to the second timing domain may include, for example, command and/or address signals. The first and second timing domains need not have any predetermined phase relationship. By at least partially decoding the signals during the transfer between the first and the second timing domains, the latency introduced by the timing domain transfer is employed for a useful purpose.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.