High performance flipchip package that incorporates heat removal with minimal thermal mismatch
US7061102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2001 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.