Apparatus and method for calibrating a semiconductor test system
US7061227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Jun 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A process and device for calibrating a semiconductor component test system includes a first connection, at which a corresponding signal, in particular a calibration signal can be input, and a second and third connection, at which the signal, in particular a calibration signal, can be emitted. The first connection is and/or can be connected via a corresponding line to a first switching apparatus, which is and/or can be connected to the second connection. A second switching apparatus is and/or can be connected to the third connection. Advantageously, the signal is then transferred to the second connection, and barred from the third connection by the first switching apparatus being closed and the second switching apparatus being opened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.