Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events
US7062606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Jun 2, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected high-use threads. The processor executes general (non-selected) threads by reading instructions from an inexpensive external memory, e.g., by way of an on-chip standard cache memory, or using other potentially slow, non-deterministic operation such as direct execution from that external memory that can cause the processor to stall while waiting for instructions to arrive. When a cache miss or other blocking event occurs during execution of a general thread, the processor switches to the pre-selected thread, whose execution with zero or minimal delay is guaranteed by the deterministic memory, thereby utilizing otherwise wasted processor cycles until the blocking event is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.