Patent · US Expired

System for testing fast synchronous digital circuits, particularly semiconductor memory chips

US7062690B2 · kind B2 · utility

1Cited by

6References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Wolfgang Ernst · Munich, DE
Gunnar Krause · Munich, DE
Justus Kuhn · Birkenfeld, DE
Jens Lüpke · Hersbruck, DE
Jochen Müller · Hersbruck, DE
Peter Pöchmüller · Birkenfeld, DE
Michael Schittenhelm · Poing, DE

Key dates

Filing date	Jul 18, 2001
Grant date	Jun 13, 2006
Priority date	—
Expiry date	Dec 24, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/56
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.