Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization
US7062729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Sep 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.