Heater for annealing trapped charge in a semiconductor device
US7064414B2 · kind B2 · utility
5Cited by
5References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.