Combination field programmable gate array allowing dynamic reprogrammability
US7064973B2 · kind B2 · utility
45Cited by
98References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Dec 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.