Multi-layer overlay measurement and correction technique for IC manufacturing
US7065737B2 · kind B2 · utility
33Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Apr 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.