Method of integrating optical devices and electronic devices on an integrated circuit

US7067342B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Omar Zia · Austin, US
• Nigel G. Cave · Austin, US
• Lawrence C. Gunn, III · Encinitas, US

Key dates

• Filing date: Nov 15, 2004
• Grant date: Jun 27, 2006
• Expiry date: Nov 15, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01

Abstract

A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.