Recessed channel with separated ONO memory device
US7067377B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
Abstract
Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.