Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit
US7068072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.