Resistive memory cell configuration and method for sensing resistance values
US7068533B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines. A plurality of resistive memory cells being disposed in a memory matrix form between said first and second current lines, said first current lines defining the columns of said memory matrix form, while said second current lines defining the rows of it, wherein each one of the resistive memory cells being connected to one of said first current lines; a plurality of selection transistors having gates and drain-source paths, each drain-source path of said selection transistors being connected to a multiplicity of the resistive memory cells of a row of said memory matrix, said drain-source paths of different selection transistors being connected to a fourth current line (SL), the gates of said selection transistors of a row of said memory matrix form being connected to one of said third current lines. It further relates to a method for sensing the resistance values of a selected resistive memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.