Flash memory with low tunnel barrier interpoly insulators

US7068544B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Leonard Forbes · Corvallis, US
• Jerome M. Eldridge · Los Gatos, US

Key dates

• Filing date: Aug 30, 2001
• Grant date: Jun 27, 2006
• Expiry date: Dec 16, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/681

Abstract

Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.