Method for forming a single instruction multiple data massively parallel processor system on a chip
US7069416B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7821
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings between a PE sub-array and its associated memory stripe are managed by placing the PE sub-arrays so that their data paths run at right angle to the data paths of the plurality of memory stripes. The data lines exiting the memory stripes are run across the PE sub-arrays on one metal layer. At the appropriate locations, the data lines are coupled to another orthogonally oriented metal layer to complete the coupling between the memory stripe and its associated PE sub-array. The plurality of PE sub-arrays are mapped to form a large logical array, in which each PE is coupled to four other PEs. Physically distant PEs are coupled using current mode differential logical couplings an drivers to insure good signal integrity at high operational speeds. Each PE contains a small DRAM register array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.