Silicon rich barrier layers for integrated circuit devices
US7071049B2 · kind B2 · utility
7Cited by
4References
55Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 30, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Dec 28, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.