Voltage-controlled analog delay locked loop
US7071745B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch generates three signals that are received by the delay voltage control: a “latched slow signal”, a “latched fast signal”, as well as a “latched fast to slow signal”. The phase detector generates “go fast” and “go slow” signals that are received by the fast/slow latch. The analog delay locked loop sets the initial delay of the delay line at or near its minimum value on start-up. The delay is then forced to increase from the minimum value until a locking condition is achieved independent of the phase relationship between the reference and delayed clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.