Microprocessor including cache memory supporting multiple accesses per cycle
US7073026B2 · kind B2 · utility
9Cited by
6References
51Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | May 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of independently accessible storage blocks. The buses may be coupled to convey a plurality of cache access requests to each of the storage blocks. In response to the plurality of cache access requests being conveyed on the plurality of cache buses, different ones of the storage blocks are concurrently accessible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.