Providing a register file memory with local addressing in a SIMD parallel processor
US7073039B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Sep 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time. In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.