Method for testing embedded DRAM arrays
US7073100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2002 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Feb 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.