Routing vias in a substrate from bypass capacitor pads
US7075185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0979
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.