Semiconductor memory device and layout method thereof
US7075849B2 · kind B2 · utility
1Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | May 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.