Methodology of locating faults of scan chains in logic integrated circuits
US7076707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Aug 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
For a plurality of logic integrated circuits, initial value vectors associated with flip-flops are retrieved from each of corresponding scan chain sets. The initial value vectors of the same corresponding scan chain set are compared with each other so as to identify elements with fixed values in the initial value vectors. When the total number of the elements with fixed values reaches a predetermined percentage, the elements having fixed values are selected as a golden pattern of the corresponding scan chain set. During the testing, an initial value vector of a scan chain of a logic integrated circuit to be tested is compared with the golden pattern associated with the scan chain, so as to determine whether a faulty flip-flop exists in the scan chain of the logic integrated circuit to be tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.