Patent · US Expired

Semiconductor wafer with improved local flatness, and method for its production

US7077726B2 · kind B2 · utility

7Cited by

5References

3Claims

0Family size

Assignee

Siltronic AG · DE

Inventors

Georg Pietsch · Burghausen, DE
Michael Kerstan · Burghausen, DE
Anton Huber · Burghausen, DE

Key dates

Filing date	Jul 31, 2002
Grant date	Jul 18, 2006
Priority date	—
Expiry date	Jul 17, 2023

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P70/50
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A process for producing semiconductor wafers comprises simultaneous grinding of both sides of the semiconductor wafers in a single step, 1S-DDG, wherein this grinding is the only material-removing mechanical machining step which is used to machine the surfaces of the semiconductor wafers. This process produces semiconductor wafers with improved geometry and nanotopology.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.