Method for fabricating an integrated semiconductor circuit to prevent formation of voids
US7078313B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2002 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Mar 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.