Methods for the optimization of substrate etching in a plasma processing system
US7078350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2004 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Sep 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer. The method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the second etchant has a low selectivity to the second hard mask material of the second hard mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.