Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same

US7078748B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Matthias Goldbach · Dresden, DE
• Frank Jakubowski · Dresden, DE
• Ralf Koepe · Dresden, DE
• Chao-Wen Lay · Gongguan, TW
• Kristin Schupke · Dresden, DE
• Michael J. Schmidt · Queen Creek, US
• Cheng-Chih Huang · Taipei, TW

Key dates

• Filing date: Jun 14, 2004
• Grant date: Jul 18, 2006
• Expiry date: Jul 3, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/28044
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of t…