Wafer level burn-in of SRAM
US7079433B1 · kind B1 · utility
3Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 18, 2001 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jul 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.