On-chip service processor
US7080301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2005 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Oct 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.