Concurrent measurement of critical dimension and overlay in semiconductor manufacturing
US7080330B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | May 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N21/956
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.