Methods of selectively bumping integrated circuit substrates and related structures
US7081404B2 · kind B2 · utility
29Cited by
183References
51Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2004 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Mar 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Bumping a substrate having a metal layer thereon may include forming a barrier layer on the substrate including the metal layer and forming a conductive bump on the barrier layer. Moreover, the barrier layer may be between the conductive bump and the substrate, and the conductive bump may be laterally offset from the metal layer. After forming the conductive bump, the barrier layer may be removed from the metal layer thereby exposing the metal layer while maintaining a portion of the barrier layer between the conductive bump and the substrate. Related structures are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.