Gate dielectric structure for reducing boron penetration and current leakage
US7081419B2 · kind B2 · utility
3Cited by
14References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2004 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | May 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor device capable of substantially retarding boron penetration within the semiconductor device and a method of manufacture therefor. In the present invention the semiconductor device includes a gate dielectric located over a substrate of a semiconductor wafer, wherein the gate dielectric includes a nitrided layer and a dielectric layer. The present invention further includes a nitrided transition region located between the dielectric layer and the nitrided layer and a gate located over the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.